US 12,438,042 B2
High capacitance MIM device with self aligned spacer
Hsuan-Han Tseng, Tainan (TW); Chun-Yuan Chen, Tainan (TW); Lu-Sheng Chou, Tainan (TW); Hsiao-Hui Tseng, Tainan (TW); and Jhy-Jyi Sze, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/366,120.
Application 18/366,120 is a division of application No. 17/352,812, filed on Jun. 21, 2021, granted, now 11,984,353.
Claims priority of provisional application 63/145,879, filed on Feb. 4, 2021.
Prior Publication US 2023/0377957 A1, Nov. 23, 2023
Int. Cl. H10D 1/00 (2025.01); H01L 21/768 (2006.01); H10D 1/68 (2025.01)
CPC H01L 21/76832 (2013.01) [H01L 21/76831 (2013.01); H10D 1/043 (2025.01); H10D 1/714 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A metal-insulator-metal (MIM) capacitor structure, comprising:
one or more lower interconnects disposed within a lower dielectric structure over a substrate;
a first dielectric layer over the lower dielectric structure, wherein the first dielectric layer comprises inner sidewalls defining a plurality of openings extending through the first dielectric layer;
a lower electrode arranged along the inner sidewalls and over an upper surface of the first dielectric layer;
a capacitor dielectric arranged along inner sidewalls and an upper surface of the lower electrode;
an upper electrode arranged along inner sidewalls and an upper surface of the capacitor dielectric; and
a spacer along outermost sidewalls of the lower electrode and along outermost sidewalls of the capacitor dielectric, wherein the spacer has an inner sidewall spaced apart from an outermost sidewall of the upper electrode.