| CPC H01L 21/76832 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5329 (2013.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, the method comprising:
forming a first interconnect level over a substrate, the first interconnect level comprising a dielectric layer and a first conductive feature through the dielectric layer;
depositing an inhibitor cap on a top surface of the first conductive feature, wherein a top surface of the dielectric layer remains exposed after depositing the inhibitor cap;
forming an etch-resistant layer on the top surface of the dielectric layer, wherein a top surface of the inhibitor cap remains exposed after forming the etch-resistant layer;
depositing an etch stop layer (ESL) over the etch-resistant layer and the inhibitor cap;
removing the inhibitor cap with a plasma treatment, wherein after removing the inhibitor cap, an air gap remains between the first conductive feature and the ESL; and
forming a second interconnect level over the first interconnect level, wherein a conductive via of the second interconnect level extends through the ESL to the top surface of the first conductive feature.
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