US 12,438,040 B2
Method for preparing semiconductor device with air gap
Liang-Pin Chou, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 22, 2023, as Appl. No. 18/200,095.
Application 17/343,360 is a division of application No. 16/561,562, filed on Sep. 5, 2019, granted, now 11,114,334.
Application 18/200,095 is a continuation in part of application No. 17/343,360, filed on Jun. 9, 2021, granted, now 11,705,364.
Prior Publication US 2023/0298933 A1, Sep. 21, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 12/34 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for preparing a semiconductor device, comprising:
forming a first dielectric structure and a second dielectric structure over a semiconductor substrate;
forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure;
partially removing the conductive material to form a first bit line and a second bit line in the first opening;
forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively;
forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and
forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.