US 12,438,038 B2
Forming vias in a semiconductor device
Kaushik Kumar, Hoegaarden (BE); Yannick Feurprier, Brussels (BE); and Zsolt Tökei, Leuven (BE)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP); and IMEC VZW, Leuven (BE)
Filed by Tokyo Electron Limited, Tokyo (JP); and IMEC VZW, Leuven (BE)
Filed on Apr. 6, 2021, as Appl. No. 17/223,876.
Claims priority of provisional application 63/006,338, filed on Apr. 7, 2020.
Prior Publication US 2021/0313217 A1, Oct. 7, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76816 (2013.01) [H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a vertical electrical interconnect, the method comprising:
forming a first metallization layer on a substrate, the first metallization layer having lines of metal running parallel to a working surface of the substrate;
forming a first metal-containing etch stop layer on the first metallization layer;
forming openings in the first metal-containing etch stop layer using a first supervia mask, wherein the first supervia mask comprises a first mask opening having a first width;
forming a second metallization layer on the substrate over the first metal-containing etch stop layer;
forming a second metal-containing etch stop layer on the second metallization layer;
forming openings in the second metal-containing etch stop layer using a second supervia mask, wherein the second supervia mask comprises a second mask opening having the first width;
forming a third metallization layer on the substrate over the second metal-containing etch stop layer;
forming a third supervia mask over the substrate, wherein the third supervia mask comprises a third mask opening having the first width; and
etching a supervia opening from the third metallization layer to the first metallization layer using the third supervia mask as an etch mask, wherein the supervia opening exposes the first metal-containing etch stop layer and the second metal-containing etch stop layer, and wherein a second width of the supervia opening at the first metal-containing etch stop layer is less than a third width of the supervia opening at the second metal-containing etch stop layer.