US 12,438,037 B2
Manufacturing method of semiconductor structure
Kuo Hsiung Chen, Hsinchu County (TW); Ya-Ting Chen, Hsinchu County (TW); Chun-Ta Chen, Taichung (TW); Chang Tsung Lin, Taichung (TW); and Shih-Ping Lee, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Jan. 31, 2023, as Appl. No. 18/162,635.
Claims priority of application No. 112100055 (TW), filed on Jan. 3, 2023.
Prior Publication US 2024/0222189 A1, Jul. 4, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76808 (2013.01) [H01L 21/76813 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a first conductive layer in the first dielectric layer;
forming a capping layer on the first dielectric layer and the first conductive layer, wherein a material of the capping layer is nitride;
forming a diffusion barrier layer covering the capping layer, wherein a material of the diffusion barrier layer is silicon-rich oxide;
forming a second dielectric layer on the diffusion barrier layer;
forming an opening in the second dielectric layer, wherein the opening exposes the diffusion barrier layer;
forming a patterned photoresist layer on the second dielectric layer; and
performing a patterning process by using the patterned photoresist layer as a mask to expand the opening and to expose the first conductive layer.