US 12,438,035 B2
Semiconductor device and method for manufacturing the same
Mitsuhide Kori, Kyoto (JP); and Yuji Matsumoto, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/794,867
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Mar. 4, 2021, PCT No. PCT/JP2021/008507
§ 371(c)(1), (2) Date Jul. 22, 2022,
PCT Pub. No. WO2021/187145, PCT Pub. Date Sep. 23, 2021.
Claims priority of application No. 2020-048038 (JP), filed on Mar. 18, 2020.
Prior Publication US 2023/0054315 A1, Feb. 23, 2023
Int. Cl. H01L 21/76 (2006.01); H01L 21/762 (2006.01); H10D 30/60 (2025.01); H10D 62/40 (2025.01)
CPC H01L 21/76232 (2013.01) [H10D 30/60 (2025.01); H10D 62/405 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an Si chip which has a main surface facing a {100} plane;
a trench which is formed by digging down the main surface and has an open end extending inclined in a <110> direction side with respect to a <100> direction in a plan view, and which demarcates a device region in the main surface by the open end;
an oxide film which is constituted of an oxide of the Si chip and formed as a film on the main surface and at the open end in the device region, and which is constituted of a gate oxide film;
a drain region which is formed in a region on one side with respect to the oxide film in a surface layer portion of the main surface in the device region;
a source region which is formed in a region on another side with respect to the oxide film in the surface layer portion of the main surface in the device region to define a channel with the drain region; and
a gate electrode which is formed on the oxide film and faces the channel across the oxide film.