US 12,438,034 B2
Narrowing single diffusion break
Ruilong Xie, Niskayuna, NY (US); Veeraraghavan S. Basker, Schenectady, NY (US); Kangguo Cheng, Schenectady, NY (US); and Junli Wang, Slingerlands, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 20, 2021, as Appl. No. 17/645,236.
Prior Publication US 2023/0197503 A1, Jun. 22, 2023
Int. Cl. H10D 30/62 (2025.01); H01L 21/762 (2006.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/76224 (2013.01) [H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first active region comprising a first transistor with a first gate disposed on a substrate;
a second active region comprising a second transistor with a second gate disposed on the substrate;
a diffusion break region disposed between the first and second active regions, the diffusion break region comprising a diffusion break that extends into the substrate and has a width that is less than widths of the first and second gates; and
a first spacer liner contacting sides of the first and second gates;
a second spacer liner contacting (i) the first spacer liner, wherein the first and second spacer liners both contact the sides of the diffusion break, wherein a width of the second spacer liner and the diffusion break define a total width of the diffusion break region, and wherein the second spacer liner contacts source/drain (S/D) regions in the first active region and the second active region; and
wherein the diffusion break region further comprises:
portions of channels disposed along the sides of the diffusion break, wherein the portions of the channels are disposed underneath the second spacer liner and contact the S/D regions.