US 12,438,000 B2
Methods for integrated circuit design and fabrication
Tsong-Hua Ou, Taipei (TW); Ken-Hsien Hsieh, Taipei (TW); Shih-Ming Chang, Hsinchu County (TW); Wen-Chun Huang, Taipei (TW); Chih-Ming Lai, Hsinchu (TW); Ru-Gun Liu, Hsinchu County (TW); and Tsai-Sheng Gau, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 22, 2021, as Appl. No. 17/181,915.
Application 16/542,790 is a division of application No. 15/852,129, filed on Dec. 22, 2017, granted, now 10,410,863, issued on Sep. 10, 2019.
Application 15/174,131 is a division of application No. 14/262,432, filed on Apr. 25, 2014, granted, now 9,362,119, issued on Jun. 7, 2016.
Application 17/181,915 is a continuation of application No. 16/542,790, filed on Aug. 16, 2019, granted, now 10,930,505.
Application 15/852,129 is a continuation of application No. 15/174,131, filed on Jun. 6, 2016, granted, now 9,852,908, issued on Dec. 26, 2017.
Prior Publication US 2021/0175081 A1, Jun. 10, 2021
Int. Cl. H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/0338 (2013.01) [H01L 21/0274 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/32139 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first pattern feature directly on a material layer by a first photolithographic process, the first pattern feature formed of the same material throughout the first pattern feature, wherein a top surface of the first pattern feature is exposed after the forming of the first pattern feature over the material layer by the first photolithographic process, the top surface of the first pattern feature facing away from the material layer;
forming a first spacer feature on a first sidewall of the first pattern feature and a second spacer feature on a second sidewall of the first pattern feature, the second sidewall opposing the first sidewall, wherein bottom surfaces of the first pattern feature and the second pattern feature are formed on an upper surface of the material layer, wherein a topmost surface of the first spacer feature or topmost surface of the second spacer feature is coplanar with a topmost surface of the first pattern feature;
removing a first portion of the first pattern feature, without removing any of the first spacer feature or the second spacer feature, to expose the material layer, wherein after removing the first portion of the first pattern feature a remaining portion of the first pattern feature remains disposed on the first and second spacer features; and
patterning the material layer using the remaining portion of the first pattern feature as a mask.