US 12,437,915 B2
Simple litz planar architecture with minimal vias to reduce AC resistance
Subhash Joshi Tharayparambil George, Kerala (IN); Renji Varghese Chacko, Kerala (IN); Akhila Elappully Manikandan, Kerala (IN); Seena Somarajan, Kerala (IN); Vinod John, Karnataka (IN); and Anurag Singh, Karnataka (IN)
Assigned to CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING (C-DAC), Thiruvananthapuram (IN); and INDIAN INSTITUTE OF SCIENCE (IISC), Bangalore (IN)
Filed by CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING (C-DAC), Thiruvananthapuram (IN); and Indian Institute of Science (IISc), Karnataka (IN)
Filed on Apr. 10, 2023, as Appl. No. 18/297,673.
Claims priority of application No. 202241021129 (IN), filed on Apr. 8, 2022.
Prior Publication US 2023/0352235 A1, Nov. 2, 2023
Int. Cl. H01F 38/14 (2006.01); H05K 1/11 (2006.01)
CPC H01F 38/14 (2013.01) [H05K 1/116 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A simple litz planar structure for reducing Alternating Current (AC) resistance, the simple litz planar structure comprising:
a plurality of conductor strands (S1-S8) of a first layer (101);
a plurality of conductor strands (S1-S8) of a second layer (103);
wherein the first layer (101) and the second layer (103) are separated by an insulating layer (105); and
a plurality of vias set (V1-V8), wherein each vias set is configured to perform transposition between a corresponding conductor strand of the first layer (101) and a conductor strand of the second layer (103), wherein each vias set comprises more than one vias.