US 12,437,833 B2
Stacked integrated circuit
Dong Uk Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 7, 2023, as Appl. No. 18/331,012.
Application 18/331,012 is a continuation in part of application No. 17/893,806, filed on Aug. 23, 2022.
Claims priority of application No. 10-2022-0062933 (KR), filed on May 23, 2022.
Prior Publication US 2023/0377679 A1, Nov. 23, 2023
Int. Cl. G11C 29/00 (2006.01)
CPC G11C 29/785 (2013.01) [G11C 29/76 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A chip comprising:
an even through via, through which an even address is received, and an even redundancy through via, through which an even redundancy address is received; and
an odd through via, through which an odd address is received, and an odd redundancy through via, through which an odd redundancy address is received;
an even address selection circuit configured to generate a selection even address and a selection even redundancy address based on a chip information signal, the even address, the even redundancy address, the odd address, and the odd redundancy address; and
an even internal address generation circuit configured to generate an internal even address based on an even repair signal, the selection even address, and the selection even redundancy address;
an odd address selection circuit configured to generate a selection odd address and a selection odd redundancy address based on the chip information signal, the even address, the even redundancy address, the odd address, and the odd redundancy address;
wherein the even through via, the even redundancy through via, the even address selection circuit and the even internal address generation circuit are disposed in an even area; and
wherein the odd through via, the odd redundancy through via, and the odd address selection circuit are disposed in an odd area.