US 12,437,832 B2
Repair techniques for coupled memory dies
James Brian Johnson, Boise, ID (US); Brent Keeth, Boise, ID (US); Kunal R. Parekh, Boise, ID (US); Eiichi Nakano, Boise, ID (US); and Amy Rae Griffin, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,403.
Claims priority of provisional application 63/386,695, filed on Dec. 9, 2022.
Prior Publication US 2024/0194287 A1, Jun. 13, 2024
Int. Cl. G11C 29/52 (2006.01); G11C 29/02 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 29/022 (2013.01); G11C 29/025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first semiconductor die, comprising:
a first memory array comprising a plurality of first memory cells;
a plurality of first contacts each associated with data signaling for a respective subset of first memory cells of the plurality of first memory cells;
a second memory array comprising a plurality of second memory cells; and
a plurality of second contacts each associated with data signaling for a respective subset of second memory cells of the plurality of second memory cells; and
a second semiconductor die coupled with the first semiconductor die, comprising:
a plurality of third contacts each corresponding to a respective first contact of the plurality of first contacts;
a plurality of fourth contacts each corresponding to a respective second contact of the plurality of second contacts; and
circuitry coupled with the plurality of third contacts and the plurality of fourth contacts, and configured to couple a data path with a third contact of the plurality of third contacts or a fourth contact of the plurality of fourth contacts based at least in part on an error condition of the data signaling associated with a first contact of the plurality of first contacts corresponding to a third contact of the plurality of third contacts.