US 12,437,831 B2
Non-volatile memory with slow voltage ramp compensation
Sai Gautham Thoppa, San Jose, CA (US); Parth Amin, Livermore, CA (US); and Long Pham, San Ramon, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 26, 2023, as Appl. No. 18/359,816.
Claims priority of provisional application 63/492,229, filed on Mar. 25, 2023.
Prior Publication US 2024/0321379 A1, Sep. 26, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/12005 (2013.01); G11C 29/12015 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a signal line;
a plurality of non-volatile memory cells connected to the signal line; and
a control circuit connected to the signal line and the non-volatile memory cells, the control circuit is configured to program the memory cells by raising a voltage applied to the signal line to a program voltage during a first time period and applying the program voltage to the memory cells via the signal line during a second time period after the first time period, the control circuit is further configured to perform testing during the first time period of the voltage applied to the signal line and elongate the first time period during the first time period based on the testing, the testing comprises determining during the first time period whether the voltage applied to the signal line is greater than an intermediate voltage that is lower than the program voltage, the control circuit is configured to elongate the first time period by adding extra time to the first time period if the voltage applied to the signal line is determined during the testing to be not greater than the intermediate voltage.