| CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/44 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01)] | 20 Claims |

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1. A memory system, comprising:
a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells; and
a memory controller configured to:
execute a first operation in response to a first read request from a host device, the first read request specifying a first logical address corresponding to a first cell unit included in a target group of the plurality of groups; and
execute a second operation in response to a second read request from the host device, the second read request specifying a second logical address corresponding to a second cell unit different from the first cell unit included in the target group, wherein
the first operation includes:
based on a first correction amount associated with the target group, reading first data from the first cell unit;
executing error correction on the first data;
calculating a second correction amount based on the first data and error-corrected first data; and
updating the first correction amount to the second correction amount, and
the second operation includes:
reading second data from the second cell unit;
executing error correction on the second data;
calculating a third correction amount based on the second data and error-corrected second data;
converting the third correction amount into a fourth correction amount; and
updating the first correction amount to the fourth correction amount.
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