US 12,437,829 B2
Apparatuses, systems, and methods for storing error information and providing recommendations based on same
Sujeet Ayyapureddi, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 7, 2024, as Appl. No. 18/598,899.
Claims priority of provisional application 63/490,059, filed on Mar. 14, 2023.
Prior Publication US 2024/0312550 A1, Sep. 19, 2024
Int. Cl. G11C 29/42 (2006.01)
CPC G11C 29/42 (2013.01) 20 Claims
OG exemplary drawing
 
4. An apparatus comprising:
a memory array comprising a plurality of word lines, a plurality of bit lines configured to receive a plurality of column select signals, and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines;
a fuse array configured to store baseline error information for the plurality of word lines of the memory array; and
a command decoder configured to decode the baseline error information stored in the fuse array to load the baseline error information into the memory array, wherein the memory array comprises a plurality of banks and the apparatus further comprises a plurality of state machines, wherein individual ones of the plurality of state machines are associated with different ones of the plurality of banks, the individual ones of the plurality of state machines configured to cause the baseline error information received from the command decoder to be written to the word lines of a corresponding bank of the plurality of banks.