US 12,437,828 B2
Systems and methods for monitoring and managing memory devices
Syed M. Alam, Austin, TX (US); Jason Janesky, Gilbert, AZ (US); Han Kyu Lee, Chandler, AZ (US); Hamid Almasi, Chandler, AZ (US); Pedro Sanchez, Chandler, AZ (US); Cristian P. Masgras, Round Rock, TX (US); Iftekhar Rahman, Chandler, AZ (US); Sumio Ikegawa, Phoenix, AZ (US); Sanjeev Aggarwal, Scottsdale, AZ (US); Dimitri Houssameddine, Sunnyvale, CA (US); and Frederick Charles Neumeyer, Austin, TX (US)
Assigned to Everspin Technologies, Inc., Chandler, AZ (US)
Filed by Everspin Technologies, Inc., Chandler, AZ (US)
Filed on Sep. 15, 2023, as Appl. No. 18/467,996.
Application 18/467,996 is a continuation of application No. 17/512,392, filed on Oct. 27, 2021, granted, now 11,798,646.
Claims priority of provisional application 63/107,173, filed on Oct. 29, 2020.
Prior Publication US 2024/0006011 A1, Jan. 4, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array including a two-layer orthogonal error correction code (ECC), wherein a second layer of the two-layer ECC is configured to:
determine a number of bits that fail in one or more first-layer ECC words; and
if the determined number of bits that fail meets a predetermined threshold, trigger a built-in self repair (BISR) feature of the two-layer orthogonal ECC that corrects the failed bits in the one or more first-layer ECC words.