US 12,437,827 B2
DRAM specific interface calibration via programmable training sequences
Anwar Kashem, Boxborough, MA (US); Craig Daniel Eaton, Austin, TX (US); and Pouya Najafi Ashtiani, Munich (DE)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2021, as Appl. No. 17/564,327.
Prior Publication US 2023/0207038 A1, Jun. 29, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 29/36 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/36 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for training, by a sequencer of a memory interface system, an interface with dynamic random-access memory (DRAM), comprising:
scheduling a command sequence, including DRAM commands and control and status register (CSR) commands, at least one of the CSR commands configured to command a write of an operational parameter to a register of an internal datapath of the interface, the operational parameter comprising a voltage parameter of the internal datapath of the interface or a timing parameter of the internal datapath of the interface;
executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through the internal datapath of the interface and the CSR commands are written to the register of the internal datapath of the interface; and
training the interface based on an exchange of data, carried out by the DRAM commands, the training including adjustments to the operational parameter.