US 12,437,825 B2
At-speed transition fault testing for a multi-port and multi-clock memory
Tanuj Kumar, Noida (IN); Hitesh Chawla, Noida (IN); Bhupender Singh, New Delhi (IN); Harsh Rawat, Haryana (IN); Kedar Janardan Dhori, Ghaziabad (IN); Manuj Ayodhyawasi, Noida (IN); Nitin Chawla, Noida (IN); and Promod Kumar, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jul. 31, 2023, as Appl. No. 18/228,118.
Claims priority of provisional application 63/411,683, filed on Sep. 30, 2022.
Prior Publication US 2024/0112748 A1, Apr. 4, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 29/32 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/12015 (2013.01); G11C 29/32 (2013.01); G11C 2029/1204 (2013.01)] 40 Claims
OG exemplary drawing
 
1. An integrated circuit system, comprising:
a memory circuit having: a memory array, a control circuit coupled to an address port, and input/output circuits coupled to a data input port and a data output port;
wherein the control circuit includes an address register configured to latch a read address in response to a read clock;
wherein each input/output circuit includes a first data path controlled by a write clock and coupling a data input of the data input port to a write bit line of the memory array and a second data path controlled by the read clock and coupling a read bit line of the memory array to a data output of the data output port;
wherein the second data path in each input/output circuit comprises a multiplexer circuit having a first input coupled to the read bit line, a second input coupled to a bypass path and an output coupled to the data output;
wherein a test bit is applied responsive to the read clock to the second input of the multiplexer in each input/output circuit; and
wherein the multiplexer is controlled to select the second input during a testing operation.