| CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/20 (2023.02)] | 15 Claims |
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1. A semiconductor device structure, comprising:
a first transistor;
a second transistor, wherein the first transistor and the second transistor are electrically connected in parallel;
a third transistor;
a first gate structure extending along a first direction, wherein the first transistor is electrically connected to the first gate structure;
a second gate structure extending along the first direction, wherein the second transistor is electrically connected to the second gate structure;
a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, wherein the first active region is electrically connected to the third transistor; and
a first conductive element extending along the second direction and disposed on the first active region, wherein the first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed to decrease a first resistance between the first active region and the third transistor,
a first contact structure electrically connected to the active region and electrically connected to the third transistor through the first conductive element,
a second contact structure electrically connected to the active region and electrically connected to the third transistor through the first conductive element,
wherein the first gate structure and the first active region are electrically connected with each other to form a first fuse element, and the second gate structure and the first active region are electrically connected with each other to form a second fuse element;
wherein the first gate structure forms a first terminal of first fuse element to electrically connect to the first transistor whereas the first active region forms a second terminal of the first fuse element to electrically connect to the third transistor,
wherein the second gate structure forms a first terminal of second fuse element to electrically connect to the second transistor whereas the first active region forms a second terminal of the second fuse element to electrically connect to the third transistor.
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