US 12,437,820 B2
Memory including thermal anneal circuits and methods for operating the same
Hang-Ting Lue, Hsinchu (TW); Teng-Hao Yeh, Hsinchu (TW); and Wei-Chen Chen, Taoyuan (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on May 18, 2023, as Appl. No. 18/199,308.
Prior Publication US 2024/0386976 A1, Nov. 21, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/3495 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/30 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of memory cells;
a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells, the group of memory cells including multiple three-dimensional (3D) stacks of memory cells having multiple levels;
a capacitor;
a circuit to cause discharge of the capacitor via the resistive component; and
a decoder to connect the capacitor to selected resistive components of a plurality of resistive components including the resistive component,
wherein the resistive component includes upper heating plates located above the 3D stacks of memory cells, lower heating plates located below the 3D stacks of memory cells and conductive vertical pillars connecting the upper heating plates to the lower heating plates, wherein an arrangement of the upper heating plates, the lower heating plates and the conductive vertical pillars provides a single continuous snake-shaped heating element to provide heat to each 3D stack of memory cells of the group of memory cells in thermal communication with the resistive component.