US 12,437,819 B2
Memory device with current measure for calculating inhibit cells
Seung Geun Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 15, 2023, as Appl. No. 18/317,670.
Claims priority of application No. 10-2022-0152833 (KR), filed on Nov. 15, 2022.
Prior Publication US 2024/0161841 A1, May 16, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/12 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/12 (2013.01); G11C 16/24 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block including memory cells;
a voltage generator connected to the memory cells through word lines and configured to apply a program voltage or a verify voltage to the word lines;
a plurality of page buffers connected to the memory cells through a plurality of bit lines and configured to apply a program allowable voltage or a program inhibit voltage to the plurality of bit lines;
a current measurer configured to output a total current value of the plurality of bit lines according to a sensing voltage measured from the plurality of bit lines; and
a logic circuit configured to control the voltage generator and the page buffers to calculate a number of inhibit cells according to the total current value and configured to omit a verify operation of a program loop or perform the verify operation of the program loop according to the number of the inhibit cells.