US 12,437,818 B2
Corrective program verify operation with improved read window budget retention
Ching-Huang Lu, Fremont, CA (US); Hong-Yan Chen, San Jose, CA (US); and Yingda Dong, Los Altos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 14, 2023, as Appl. No. 18/233,420.
Claims priority of provisional application 63/400,511, filed on Aug. 24, 2022.
Prior Publication US 2024/0071530 A1, Feb. 29, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising:
a set of target memory cells connected to a target wordline;
a first wordline and a second wordline, each adjacent to the target wordline; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a program operation to be initiated to program the set of target memory cells of the target wordline to a target programming level;
causing, during a program verify operation of the program operation, a program verify voltage level to be applied to the target wordline to verify programming of the set of target memory cells;
selecting, from a set of pass through read voltage levels, a pass through read voltage level based on the target programming level; and
causing, during the program verify operation, a pass through voltage level to be applied to at least one of the first wordline or the second wordline, wherein the pass through voltage level is the pass through read voltage level reduced by an offset value.