| CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 80/00 (2023.02); G11C 2216/02 (2013.01)] | 20 Claims |
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1. A non-volatile memory device, comprising:
an array of non-volatile memory cells comprising a plurality of blocks, each of the blocks having a NAND architecture and comprising:
a source line;
a plurality of bit lines;
a plurality of NAND strings each comprising a plurality of memory cells connected in series between the source line and a corresponding bit line;
a plurality of drain side select transistors each connected between a NAND string and the corresponding bit line, including a plurality of individually biasable distinct sets of drain side select transistors connected between a corresponding distinct sets of NAND string and the corresponding bit lines; and
a plurality of word lines along each of which is connected a corresponding memory cell of each of the NAND strings, the word lines including:
a plurality of data word lines; and
one or more select word lines positioned on the NAND strings between the data word lines and the source line, each of the one or more select word lines programmed to select a corresponding subset of one or more but less than all of the sets of NAND strings when biased at a first voltage level and to select all of the sets of NAND strings when biased at a second voltage level.
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