US 12,437,815 B2
Delayed select gate ramp-up for peak read current consumption reduction for non-volatile memory apparatus
Abhijith Prakash, Milpitas, CA (US); and Xiang Yang, Santa Clara, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Nov. 15, 2023, as Appl. No. 18/509,848.
Prior Publication US 2025/0157547 A1, May 15, 2025
Int. Cl. G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
select gate transistors for coupling to one of a drain-side and a source-side of each of a plurality of memory holes of memory cells; and
a control means coupled to the select gate transistors of the plurality of memory holes and configured to:
during a first period of time of a read operation, ramp up a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistors to a power supply voltage,
during a second period of time of the read operation following the first period of time, ramp selected ones of the plurality of word lines to a read pass voltage and unselected ones of the plurality of word lines to the read pass voltage, the read pass voltage selected to allow the memory cells connected to the plurality of word lines to conduct, and
delay ramping the voltage applied to the select gate transistors to a select gate voltage until a predetermined time after the selected ones of the plurality of word lines and the unselected ones of the plurality of word lines ramp to the read pass voltage, the select gate voltage selected to allow the select gate transistors to conduct.