| CPC G11C 13/0097 (2013.01) [G11C 13/0033 (2013.01); G11C 13/004 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01)] | 20 Claims |

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1. A method for reducing bit disturb associated with erasing memory cells of a non-volatile two-terminal resistive switching memory device, comprising:
implementing a program process on a plurality of non-volatile memory cells of an array of non-volatile two-terminal resistive switching memory cells, the plurality comprising a first non-volatile memory cell and a second non-volatile memory cell;
performing a first erase-verify process on the first and second non-volatile memory cells, further comprising:
applying an erase process to the first and second non-volatile memory cells, and
reading the first and second non-volatile memory cells to determine whether both memory cells are in an erase state;
in response to determining both memory cells are in the erase state, performing a first weak program process on the first and second non-volatile memory cells, wherein the first weak program process comprises at least one of:
a lower pulse count than the program process,
a lower voltage magnitude than the program process, or
a lower pulse duration than the program process;
performing a second erase-verify process on the first and second non-volatile memory cells, further comprising:
applying the erase process to the first and second non-volatile memory cells, and
reading the first and second non-volatile memory cells to determine whether both memory cells are in the erase state; and
perform a final read process to determine both the first and second non-volatile memory cells are in the erase state.
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