US 12,437,810 B2
Memory device performing multiplication using logical states of memory cells
Hernan Castro, Shingle Springs, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 25, 2023, as Appl. No. 18/494,652.
Claims priority of provisional application 63/385,242, filed on Nov. 29, 2022.
Prior Publication US 2024/0177772 A1, May 30, 2024
Int. Cl. G11C 7/00 (2006.01); G06F 7/544 (2006.01); G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 19/36 (2006.01)
CPC G11C 13/0069 (2013.01) [G06F 7/5443 (2013.01); G11C 19/36 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
voltage drivers configured to apply respective voltages to the memory cells, wherein each respective voltage represents a one-bit input, and wherein the voltages are applied so that the memory cells do not threshold;
a first line coupled to first memory cells storing a respective bit of a first significance, wherein the first line is configured to sum first output currents from each of the first memory cells;
a second line coupled to second memory cells storing a respective bit of a second significance, wherein the second significance is less than the first significance, and the second line is configured to sum second output currents from each of the second memory cells; and
a logic circuit configured to provide an accumulation result based on the summed first output currents and the summed second output currents.