| CPC G11C 13/0069 (2013.01) [G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01)] | 10 Claims |

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1. A programmable resistive memory element with multiple resistance states, comprising:
a resistive layer;
a first electrical contact and a second electrical contact disposed on the resistive layer; and
a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory layer to adjust a resistance of the resistive memory layer.
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