US 12,437,808 B2
Memory device and operating method thereof
Yen-Cheng Chiu, Pingtung County (TW); Win-San Khwa, Taipei (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed on Jun. 6, 2024, as Appl. No. 18/735,782.
Application 18/735,782 is a continuation of application No. 17/674,125, filed on Feb. 17, 2022, granted, now 12,033,697.
Prior Publication US 2024/0321354 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells, wherein each of the memory cells has a first terminal coupled to a reference voltage and has a second terminal coupled to a first node,
wherein when a data value stored in a first memory cell of the memory cells is greater than one, the data value is inversely proportional to a resistance of the first memory cell,
wherein the plurality of memory cells are configured to generate a voltage signal at the first node according to the resistances of the memory cells.