US 12,437,806 B2
Semiconductor device and operating method thereof
Wei-Xiang You, Kaohsiung (TW); Cheng-Yin Wang, Taipei (TW); and Szuya Liao, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,058.
Prior Publication US 2025/0006254 A1, Jan. 2, 2025
Int. Cl. G11C 11/412 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/4125 (2013.01) [H10B 10/125 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first memory cell configured to store a first data bit at a first node when the first memory cell is turned on; and
a second memory cell configured to store the first data bit when the first memory cell is turned off,
wherein the first memory cell comprises a first switch coupled to the first node,
the first switch is configured to transmit the first data bit to the second memory cell, and configured to be turned off when the first memory cell is turned off, and
the semiconductor device further comprises:
a first conductive segment configured to store the first data bit;
a first source/drain structure coupled to the first conductive segment; and
a second source/drain structure configured to receive a bit line signal corresponding to the first data bit, and disposed above the first source/drain structure along a direction,
wherein the first conductive segment is elongated along the direction to be interposed between two portions of the second source/drain structure.