| CPC G11C 11/4096 (2013.01) [H10B 12/20 (2023.02)] | 15 Claims |
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1. A semiconductor device comprising:
a memory element including
a first semiconductor pillar erected on a substrate in a vertical direction with respect to the substrate,
a first impurity region connected to a bottom of the first semiconductor pillar,
a first gate insulating layer placed in contact with a side surface of the first semiconductor pillar,
a first gate conductor layer placed in contact with the first gate insulating layer,
a second semiconductor pillar placed on and in contact with the first semiconductor pillar,
a first insulating layer placed on the first gate conductor layer and surrounding a vicinity of a boundary between the first semiconductor pillar and the second semiconductor pillar,
a second impurity region and a third impurity region placed in contact with the second semiconductor pillar and on the first insulating layer and opposed to each other in a horizontal direction,
a second gate insulating layer placed in contact with at least one of an upper surface and opposite side surfaces of the second semiconductor pillar between the second impurity region and the third impurity region in the horizontal direction, and
a second gate conductor layer placed in contact with the second gate insulating layer; and
a MOS transistor including
a third semiconductor pillar erected on the substrate in the vertical direction with respect to the substrate,
a first material layer surrounding the third semiconductor pillar and containing an insulating material or a conductor material insulated from the third semiconductor pillar,
a fourth semiconductor pillar placed on and in contact with the third semiconductor pillar,
a third gate insulating layer placed in contact at least with opposite side surfaces of the fourth semiconductor pillar,
a third gate conductor layer placed in contact with the third gate insulating layer, and
a fourth impurity region and a fifth impurity region placed in contact with a portion of the fourth semiconductor pillar and opposed to each other in the horizontal direction, the portion being not covered by the third gate insulating layer, wherein
in the vertical direction, the second semiconductor pillar has a length shorter than a length of the fourth semiconductor pillar.
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