| CPC G11C 11/4096 (2013.01) [H10B 12/20 (2023.02)] | 11 Claims |
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1. A semiconductor element memory cell comprising:
a first impurity well layer formed on a substrate;
a second impurity well layer formed in the first impurity well layer;
a semiconductor base material formed on the second impurity well layer in a vertical direction or extended in a horizontal direction of the substrate;
a first impurity region and a second impurity region provided on opposite ends of the semiconductor base material;
first and second gate insulating layers placed adjacent to each other in contact with a lateral surface of the semiconductor base material between the first impurity region and the second impurity region;
a first gate conductor layer covering part or all of the first gate insulating layer; and
a second gate conductor layer located adjacent to the first gate conductor layer and placed in contact with a lateral surface of the second gate insulating layer,
wherein positive hole groups, generated by an impact ionization phenomenon or by a gate-induced drain leakage current, are held in the semiconductor base material by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region,
a memory write operation is performed by setting a voltage of the semiconductor base material to a first data retention voltage higher than a voltage of the first impurity region and/or the second impurity region, and
a memory erase operation is performed by controlling voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer and thereby extracting a residual positive hole group out of the positive hole groups from one or both of the first impurity region and the second impurity region to set the voltage of the semiconductor base material to a second data retention voltage lower than the first data retention voltage.
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