US 12,437,803 B2
Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package
Geon Ko, Gyeonggi-do (KR); and Choung Ki Song, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 15, 2023, as Appl. No. 18/509,315.
Claims priority of application No. 10-2023-0115962 (KR), filed on Sep. 1, 2023.
Prior Publication US 2025/0078908 A1, Mar. 6, 2025
Int. Cl. G11C 11/4093 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01)
CPC G11C 11/4093 (2013.01) [H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 2225/0651 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An operation method of a buffer chip, the operation method comprising:
receiving first control signals for setting a first memory chip;
buffering the first control signals and transmitting the buffered first control signals to the first memory chip;
storing a setting value for the first memory chip in response to the first control signals;
receiving second control signals for setting a second memory chip;
buffering the second control signals and transmitting the buffered second control signals to the second memory chip;
storing a setting value for the second memory chip in response to the second control signals;
receiving third control signals for applying the setting value for the first memory chip;
buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and
applying the stored setting value for the first memory chip as a setting value of the buffer chip in response to the third control signals.