US 12,437,802 B2
Signal quality optimization method and a signal quality optimization system
Ming-Sheng Peng, Hsinchu (TW); Ting-Ying Wu, Hsinchu (TW); Shih-Hung Wang, Hsinchu (TW); and Wei-Zhi Chen, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Sep. 15, 2023, as Appl. No. 18/368,602.
Claims priority of application No. 112117079 (TW), filed on May 9, 2023.
Prior Publication US 2024/0379152 A1, Nov. 14, 2024
Int. Cl. H03K 19/00 (2006.01); G11C 11/4093 (2006.01); G11C 29/54 (2006.01); H03K 19/0175 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 29/54 (2013.01); H03K 19/0005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal quality optimization method applicable to a first circuit and a second circuit electrically connected to each other, and the signal quality optimization method comprising:
executing a ZQ calibration process on an off-chip driver (OCD) circuit of the first circuit and an on-die termination (ODT) circuit of the second circuit through a ZQ calibration circuit, so as to obtain a plurality of calibrated resistor quantities corresponding to a plurality of OCD resistances and a plurality of corrected ODT resistances, wherein a plurality of ODT-OCD resistance combinations defines relationships between the corrected ODT resistances and the OCD resistances;
configuring a processing device to perform a waveform test process for each of the ODT-OCD resistance combinations, wherein the waveform test process includes:
setting a predetermined time rule to determine an operation success condition between the first circuit and the second circuit; and
adjusting the OCD circuit according to the calibrated resistor quantity corresponding to a target ODT resistance, transmitting a group of test signals between the second circuit and the first circuit, obtaining a signal eye diagram corresponding to the group of test signals, and obtaining an adjustable resistor ratio corresponding to the target ODT resistance by performing repeated adjustments and tests;
configuring the processing device to extract the OCD resistance value with the highest adjustable resistor ratio for the different ODT resistances, so as to obtain a plurality of preferred ODT-OCD resistance combinations; and
configuring the processing device to configure the ODT circuit and the OCD circuit according to the preferred ODT-OCD resistance combinations, and performing an operation test process for multiple times on the first circuit and the second circuit, so as to obtain an optimized ODT-OCD resistance combination according to test results of the operation test process that is performed for multiple times.