US 12,437,801 B2
Comparison operations in memory
Kyle B. Wheeler, Meridian, ID (US); Troy A. Manning, Meridian, ID (US); and Richard C. Murphy, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Apr. 19, 2024, as Appl. No. 18/640,966.
Application 15/346,526 is a division of application No. 14/715,001, filed on May 18, 2015, granted, now 9,496,023, issued on Nov. 15, 2016.
Application 18/640,966 is a continuation of application No. 17/589,417, filed on Jan. 31, 2022, granted, now 11,967,361.
Application 17/589,417 is a continuation of application No. 17/098,160, filed on Nov. 13, 2020, granted, now 11,238,920, issued on Feb. 1, 2022.
Application 17/098,160 is a continuation of application No. 16/681,523, filed on Nov. 12, 2019, granted, now 10,839,892, issued on Nov. 17, 2020.
Application 16/681,523 is a continuation of application No. 15/346,526, filed on Nov. 8, 2016, granted, now 10,490,257, issued on Nov. 26, 2019.
Claims priority of provisional application 62/008,007, filed on Jun. 5, 2014.
Prior Publication US 2024/0412775 A1, Dec. 12, 2024
Int. Cl. G11C 11/4091 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 7/065 (2013.01); G11C 7/1006 (2013.01); G11C 7/1012 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor-in-memory (PIM) device, comprising:
one or more memory arrays;
one or more sense amplifiers coupled with the one or more memory arrays; and
one or more compute components coupled with the one or more sense amplifiers, the one or more compute components configured to:
perform, by a first compute component of the one or more compute components, a first compute operation using a first value stored in the one or more memory arrays and a second value stored in the one or more memory arrays;
perform, by a second compute component of the one or more compute components and in parallel with the first compute component performing the first compute operation, a second compute operation using a third value stored in the one or more memory arrays and a fourth value stored in the one or more memory arrays; and
store a result of the first compute operation and a result of the second compute operation based at least in part on performing the first compute operation and the second compute operation.