US 12,437,799 B2
Memory device and ZQ calibration method
Kai Tian, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 11, 2023, as Appl. No. 18/448,902.
Application 18/448,902 is a continuation of application No. PCT/CN2022/123921, filed on Oct. 8, 2022.
Claims priority of application No. 202210714288.3 (CN), filed on Jun. 22, 2022.
Prior Publication US 2023/0420012 A1, Dec. 28, 2023
Int. Cl. G11C 11/4076 (2006.01); G11C 7/08 (2006.01); G11C 7/22 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 7/08 (2013.01); G11C 7/22 (2013.01); G11C 2207/2254 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
two calibration resistor interfaces, the two calibration resistor interfaces being connected to a same ZQ calibration resistor,
wherein a first master chip, a plurality of stages of cascaded first slave chips, a second master chip, and a plurality of stages of cascaded second slave chips are commonly connected to the ZQ calibration resistor,
wherein each of the first master chip, the first slave chips, the second master chip, and the second slave chips is provided with a first transmission terminal and a second transmission terminal, and each of the second transmission terminals is used to transmit a ZQ flag signal,
wherein the second transmission terminal of the first master chip is connected to the first transmission terminal of a first slave chip of a first stage of the plurality of stages of cascaded first slave chips, a second transmission terminal of a first slave chip of each stage of the plurality of stages of cascaded first slave chips is connected to a first transmission terminal of a first slave chip of a next stage of the plurality of stages of cascaded first slave chips, the second transmission terminal of the second master chip is connected to the first transmission terminal of a second slave chip of a first stage of the plurality of stages of cascaded second slave chips, and a second transmission terminal of a second slave chip of each stage of the plurality of stages of cascaded second slave chips is connected to a first transmission terminal of a second slave chip of a next stage of the plurality of stages of cascaded second slave chips,
wherein the first master chip is provided with a first signal receiver, the second master chip is provided with a second signal receiver, and each of the first slave chips and the second slave chips is provided with a respective third signal receiver,
wherein, in a command mode, the first signal receiver is used to receive, at a first ZQ signal terminal, a ZQ calibration command provided by a memory, the second signal receiver is used to receive and delay the ZQ calibration command by a second ZQ signal terminal, the first master chip and the second master chip start to calibrate based on the ZQ calibration command, and the first master chip and the second master chip send their respective the ZQ flag signals by their-the second transmission terminals in response to the calibration of the first and second master chips being completed, respectively, the respective ZQ flag signal indicating that a current chip has been calibrated with the calibration resistor, and
wherein the third signal receiver of each of the first and second slave chips is used to receive a respective ZQ flag signal received by the first transmission terminal of its respective chip, each of the first slave chips and the second slave chips starts to calibrate based on the respective ZQ flag signal, and each of the first slave chips and the second slave chips sends a respective ZQ flag signal by its respective second transmission terminal in response to a respective ZQ calibration operation being completed until all the first or second slave chips have been calibrated.