| CPC G11C 11/4074 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4087 (2013.01)] | 14 Claims |
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1. A memory device comprising:
a memory cell array comprising a plurality of rows;
a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and
an interface circuit configured to:
generate the decoded row address based on decoding a plurality of bits of a row address,
transfer the decoded row address to the row decoder, and
in an idle non-power-down mode of the memory device, precharge the decoded row address that is transferred to the row decoder in response to a predetermined condition being satisfied.
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