| CPC G11C 11/40622 (2013.01) [G11C 11/40603 (2013.01); G11C 11/4085 (2013.01)] | 20 Claims |

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1. A memory device, comprising:
a controller configured to refresh at least one of a plurality of word lines during a first refresh cycle in response to a refresh signal;
a random number generator configured to generate a first number;
a number trimmer connected to the random number generator, wherein the number trimmer is configured to modify the first number to be a modified first number, wherein the modified first number is less than a first predetermined number;
a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value of the counter and start counting in response to the refresh signal; and
an address register electrically coupled to the counter and configured to store an address of a first word line being active when the counter decrements to zero,
wherein the controller is configured to access the address register to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line;
wherein the counter is configured to decrement in response to an access signal, wherein the access signal is indicative of an access to one of the plurality of word lines.
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