US 12,437,795 B2
Dynamic random access memory refresh circuit and refresh method, and proof-of-work chip
Yusheng Zhang, Beijing (CN); and Fuquan Wang, Beijing (CN)
Assigned to SUNLUNE (SINGAPORE) PTE. LTD., Beijing (CN)
Appl. No. 18/264,414
Filed by SUNLUNE (SINGAPORE) PTE. LTD., Beijing (CN)
PCT Filed Dec. 26, 2022, PCT No. PCT/CN2022/142051
§ 371(c)(1), (2) Date Aug. 5, 2023,
PCT Pub. No. WO2023/125446, PCT Pub. Date Jul. 6, 2023.
Claims priority of application No. 202111645658.4 (CN), filed on Dec. 30, 2021.
Prior Publication US 2024/0119990 A1, Apr. 11, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4087 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A Dynamic Random Access Memory (DRAM) refresh circuit, comprising:
a row address recording circuit, configured to record a row, which is accessed in a current refresh period, in a DRAM;
a refresh drive circuit, configured to perform a refresh operation when the refresh drive circuit is invoked; and
a refresh control circuit, configured to, when refresh is triggered, invoke the refresh drive circuit to refresh a row, which is not accessed in the current refresh period, in the DRAM according to a record of the row address recording circuit;
wherein that the row address recording circuit is configured to record the row, which is accessed in the current refresh period, in the DRAM, comprises:
the row address recording circuit is configured to store respective row flag bits corresponding to all rows in the DRAM, and reset all row flag bits at beginning of each refresh period, and set a corresponding row flag bit according to a row to be accessed in an access request for the DRAM.