US 12,437,793 B2
Driving method of semiconductor device
Yuki Okamoto, Kanagawa (JP); Tatsuya Onuki, Kanagawa (JP); and Takanori Matsuzaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 18/245,784
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Sep. 9, 2021, PCT No. PCT/IB2021/058181
§ 371(c)(1), (2) Date Mar. 17, 2023,
PCT Pub. No. WO2022/064308, PCT Pub. Date Mar. 31, 2022.
Claims priority of application No. 2020-158038 (JP), filed on Sep. 22, 2020.
Prior Publication US 2024/0029773 A1, Jan. 25, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2257 (2013.01) [G11C 11/2273 (2013.01); G11C 11/2293 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for driving a semiconductor device comprising a memory cell comprising a ferroelectric capacitor, comprising:
writing binary data to the memory cell in a first period;
reading the binary data from the memory cell in a second period; and
generating a polarization reversal in the ferroelectric capacitor in a third period, so that the binary data is returned to the memory cell,
wherein the memory cell comprises a first transistor, a second transistor, and a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the ferroelectric capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein in the first period and the third period, the first transistor is in an on state and the third transistor is in an off state, and
wherein in the second period, the first transistor is in an off state and the third transistor is in an on state.