US 12,437,792 B2
Data logic processing circuit integrated in a data storage circuit
Olivier Billoint, Grenoble (FR); and Laurent Grenouillet, Grenoble (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Sep. 26, 2023, as Appl. No. 18/373,231.
Claims priority of application No. 2209986 (FR), filed on Sep. 30, 2022.
Prior Publication US 2024/0112715 A1, Apr. 4, 2024
Int. Cl. G11C 11/22 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); H03K 19/20 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A data storage circuit comprising:
an array of memory cells (CMij) such that each memory cell (CMij) comprises:
a non-volatile elementary storage component (NVM) having a first electrode (EL1) and a second electrode (EL2);
a first input/output node (SL) connected to the second electrode (EL2), a second input/output node (BL), a selection node (WL); and
a selection transistor (T1) having a gate connected to the selection node (WL) and linking the first electrode (EL1) to the second input/output node (BL);
a logic processing circuit configured to carry out a logic operation having N binary data (x1, x2, x3) as operands stored in N input memory cells (CM1, CM2, CM3), with N≥2, the second input/output nodes (BL) of said input memory cells (CM1, CM2, CM3) being linked by a common bit line, the logic processing circuit comprising:
a transimpedance amplifier stage configured to supply an analogue read signal (Vs1_ao) from the voltage of the common bit line (BL), said capacitive transimpedance amplifier stage comprising:
an operational amplifier (AO) having: a first input (e1_ao) connected to the second input/output node (BL) of the input memory cells, and a second input (e2_ao) for receiving a second reference voltage (VREF0), and an output (s1_ao) for supplying said analogue read signal (Vs1_ao);
a feedback impedance (CCR) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier;
a comparator intended to compare the analogue read signal (Vs1_ao) with a first adjustable reference voltage (VREF_cmp) in order to generate a digital output signal (Vs1_cmp) corresponding to the result of the logic operation; and
a control unit configured to adjust the reference voltage (VREF_cmp) to an amplitude selected from among N distinct predetermined amplitudes (VREF1, VREF2, VREF3), depending on the type of logic operation; and
wherein:
the feedback impedance (CCR) is a capacitive impedance and the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) are of variable electric biasing ferroelectric type; or
the feedback impedance (CCR) is a resistive impedance and the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) are of variable conductive filament resistive type.