| CPC G11C 7/1093 (2013.01) [G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/1096 (2013.01)] | 11 Claims |
|
1. An apparatus, comprising:
a master die configured to communicate with a device external to the apparatus;
at least one slave die electrically coupled to the master die and configured to communicate with the master die using an inter-die bus;
wherein the master die is configured to:
receive column address data on one or more command address pins aligned with a command address clock;
store the column address data in a master die First-In First-Out (FIFO) buffer;
receive write data on one or more DQ pads aligned with a data clock;
create an internal write command aligned with the data clock;
latch the write data and the column address data at a memory array according to the internal write command instead of a command-address clock;
release the column address data from the master die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the master die;
send a first portion of the write data and the internal write command to a memory array of the master die;
send a second portion of the write data and the internal write command to the at least one slave die using the inter-die bus;
wherein the at least one slave die is configured to locally store the second portion using the internal write command to leverage the data clock in synchronizing the internal write command as a trigger for a local write operation and an availability of the corresponding second portion of the write data.
|