US 12,437,788 B2
Syndrome decoding system
Eyal En Gad, Highland, CA (US); Leon Zlotnik, Camino, CA (US); and Yoav Weinberg, Thornhill (CA)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 29, 2023, as Appl. No. 18/523,366.
Claims priority of provisional application 63/429,699, filed on Dec. 2, 2022.
Prior Publication US 2024/0185898 A1, Jun. 6, 2024
Int. Cl. G11C 7/10 (2006.01); G06F 11/10 (2006.01)
CPC G11C 7/1012 (2013.01) [G06F 11/1068 (2013.01); G11C 7/1039 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by shift circuitry, a bit string comprising a plurality of bits;
generating a shifting indicator based on a numerical difference between a first data value written to a memory array coupled to the shift circuitry and a second data value written to the memory array, wherein:
the first data value and the second data value each correspond to a layer associated with the bit string, and
one of the first data value or the second data value corresponds to a current offset value associated with the layer and the other of the first data value or the second data value corresponds to a previous offset value associated with the layer;
determining, based on the shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry;
generating a shifted bit string by performing, using the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator; and
performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.