| CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01)] | 30 Claims |
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1. A scan driver comprising a plurality of stages, wherein each of the plurality of stages includes:
a first transistor connected between an input terminal to which a start signal is applied and a first node;
a second transistor connected between the input terminal and the first node;
a third transistor connected between a first voltage input terminal to which a first voltage is applied and a second node, a gate of the third transistor connected to the first node;
a fourth transistor connected between the second node and a second voltage input terminal to which a second voltage is applied, a first gate of the fourth transistor connected to the first node;
a pull-up transistor connected between the first voltage input terminal and an output terminal, a gate of the pull-up transistor connected to the second node; and
a pull-down transistor connected between the output terminal and the second voltage input terminal, a first gate of the pull-down transistor connected to the second node,
wherein a transistor type of the third transistor and a transistor type of the fourth transistor are different each other.
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