US 12,437,723 B2
Shift register, gate driving circuit, and display apparatus
Xuehuan Feng, Beijing (CN); Yongqian Li, Beijing (CN); and Xing Yao, Beijing (CN)
Assigned to Hefei BOE Joint Technology Co., Ltd., Anhui (CN); BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/578,059
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
PCT Filed Apr. 28, 2023, PCT No. PCT/CN2023/091520
§ 371(c)(1), (2) Date Jan. 10, 2024,
PCT Pub. No. WO2024/221392, PCT Pub. Date Oct. 31, 2024.
Prior Publication US 2025/0124877 A1, Apr. 17, 2025
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01); G11C 19/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register, comprising: a display input reset circuit, an inverter circuit, at least one output circuit and a first detection circuit, wherein the display input reset circuit, the inverter circuit and the at least one output circuit are connected to a pull-up node, and the inverter circuit and the at least one output circuit are connected to a pull-down node;
the display input reset circuit is connected to a display signal input terminal, a reset signal terminal and a second power supply terminal, and is configured to write an active level signal to the pull-up node in response to a signal provided by the display signal input terminal and to write a voltage provided by the second power supply terminal to the pull-up node in response to a signal provided by the reset signal terminal;
the inverter circuit is connected to the second power supply terminal and a third power supply terminal, and is configured to invert a voltage at the pull-up node in response to a voltage provided by the second power supply terminal and an active level voltage provided by the third power supply terminal to obtain an inverted voltage, and output the inverted voltage to the pull-down node;
the at least one output circuit is connected to the pull-up node, the pull-down node, a corresponding signal output terminal, a corresponding output clock signal terminal, and a corresponding fourth power supply terminal, and is configured to write a signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the voltage at the pull-up node, and write a voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal in response to the voltage at the pull-up node; and
the first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line, and is configured to acquire a voltage at the signal acquisition point in response to a signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line, so that an external first chip adjusts an active level voltage provided by the third power supply terminal according to the detection voltage; and the signal acquisition point comprises one of the pull-down node and the signal output terminal, or comprises both the pull-down node and the signal output terminal;
wherein the first detection circuit comprises: at least one of a first detection sub-circuit and a second detection sub-circuit, the acquisition control terminal comprises: a first acquisition control terminal or a second acquisition control terminal;
the first detection sub-circuit is connected to the pull-down node, the first acquisition control terminal, and the first signal detection line, and is configured to acquire a voltage at the pull-down node in response to a signal provided by the first acquisition control terminal, and output a first detection voltage corresponding to the voltage at the pull-down node to the first signal detection line; and
the second detection sub-circuit is connected to the signal output terminal, the second acquisition control terminal, and the first signal detection line, and is configured to acquire a voltage at the pull-down node in response to a signal provided by the second acquisition control terminal, and output a second detection voltage corresponding to the voltage at the signal output terminal to the first signal detection line.