| CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01); G09G 2330/028 (2013.01); G09G 2330/12 (2013.01)] | 19 Claims |

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1. A display device, comprising:
a display panel including a plurality of pixels configured to display an image;
a gate driving circuit configured to output respective scan signals to gate lines of the display panel; and
a controller configured to (1) determine a deviation between the scan signals applied to the gate lines of the display panel and (2) compensate for the deviation when it is determined that the deviation is greater than a threshold,
wherein the gate driving circuit includes a plurality of output buffers that are commonly connected to one Q node, each of the plurality of output buffers receives a corresponding one of a plurality of scan clock signals and output a scan signal to a corresponding gate line in response to a voltage of the Q node, and
wherein the controller determines the deviation between the scan signals output from the plurality of output buffers commonly connected to one Q node, and compensate for the deviation when it is determined that the deviation is greater than the threshold by controlling Q node voltage.
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