| CPC G09G 3/3266 (2013.01) [G09G 3/3275 (2013.01); G11C 19/28 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] | 6 Claims |
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1. A display panel, comprising:
multiple stages selectively connected to lines to which multiple clock signals are supplied, wherein the multiple stages are configured to sequentially output a scan pulse,
wherein each of the multiple stages includes:
an input unit electrically connected to each of a start signal line and a clock signal line;
a Q node controller electrically connected to the input unit through a Q2 node;
an output unit electrically connected to the Q node controller through a Q node;
a voltage potential maintaining circuit electrically connected to the Q node; and
a QB node controller having one side electrically connected to the output unit through a QB node and the other side electrically connected to the output unit through a gate-off signal line,
wherein the voltage potential maintaining circuit is configured to operate based on a driving signal and maintains a voltage potential of the Q node at a value below a selected level,
wherein the output unit includes:
a pull-up transistor for outputting the scan signal to an output terminal based on a voltage level of the Q node; and
a pull-down transistor for supplying a gate-off signal to the output terminal based on a voltage level of the QB node,
wherein the pull-up transistor includes a first thin-film transistor having a gate electrode electrically connected to the Q node, a first electrode electrically connected to a gate-on signal line, and a second electrode electrically connected to the output terminal,
wherein the pull-down transistor includes a second thin-film transistor having a gate electrode electrically connected to the QB node, a first electrode electrically connected to the output terminal, and a second electrode electrically connected to the gate-off signal line.
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