| CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01)] | 9 Claims |
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1. A driver comprising:
an input circuit that transmits an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
an inverter that generates an output signal based on a voltage of the first node,
wherein each of the input circuit and the inverter includes a first transistor and a second transistor connected to each other,
an active area of the first transistor and an active area of the second transistor include different materials, and
a gate terminal of the second transistor is electrically connected to a semiconductor material spaced apart from the active area of the second transistor,
wherein the gate terminal of the second transistor includes an upper gate terminal and a lower gate terminal, and
the upper gate terminal is electrically connected to the lower gate terminal.
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