US 12,437,356 B2
Dynamically reducing latency in processing pipelines
Sau Yan Keith Li, San Jose, CA (US); Seth Schneider, San Jose, CA (US); Cody Robson, Portland, OR (US); Lars Nordskog, Corte Madera, CA (US); Charles Hansen, San Francisco, CA (US); and Rouslan Dimitrov, Santa Clara, CA (US)
Assigned to Nvidia Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Mar. 4, 2024, as Appl. No. 18/594,099.
Application 18/594,099 is a continuation of application No. 17/448,258, filed on Sep. 21, 2021, granted, now 11,922,533.
Prior Publication US 2024/0202860 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/3836 (2013.01); G06F 9/4881 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a weighted average execution time associated with each execution stage of a plurality of execution stages processing a plurality of frames starting with an initial execution stage and continuing with each subsequent execution stage;
determining a first largest weighted average execution time associated with one of the plurality of execution stages; and
applying a delay to the initial execution stage prior to processing a first next frame of the plurality of frames, wherein the delay is based on the first largest weighted average execution time of the plurality of execution stages.