US 12,437,224 B2
Noise reduced circuits for trapped-ion quantum computers
Omar Shehab, Hyattsville, MD (US); and Isaac Hyun Kim, Menlo Park, CA (US)
Assigned to IONQ, INC., College Park, MD (US)
Filed by IONQ, INC., College Park, MD (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,240.
Application 17/881,240 is a continuation of application No. 16/578,142, filed on Sep. 20, 2019, granted, now 11,455,563.
Claims priority of provisional application 62/852,264, filed on May 23, 2019.
Prior Publication US 2023/0037180 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 10/60 (2022.01); G06E 3/00 (2006.01); G06N 10/40 (2022.01)
CPC G06N 10/60 (2022.01) [G06E 3/005 (2013.01); G06N 10/40 (2022.01)] 20 Claims
OG exemplary drawing
 
1. A method of performing computation in a hybrid quantum-classical computing system comprising a classical computer and a quantum processor, comprising:
computing, by a classical computer, a model Hamiltonian onto which a selected problem is mapped, wherein the model Hamiltonian comprises a plurality of sub-Hamiltonians;
transforming a quantum processor from an initial state to a trial state based on each of the plurality of sub-Hamiltonians and an initial set of variational parameters by applying a reduced trial state preparation circuit to the quantum processor, wherein the quantum processor comprises a plurality of qubits; and
outputting, by the classical computer, an optimized solution to the selected problem, based on an expectation value of each of the plurality of sub-Hamiltonians on the quantum processor.