US 12,437,195 B2
Systems and methods for pipelined heterogeneous dataflow for artificial intelligence accelerators
Xiaoyu Sun, Hsinchu (TW); and Kerem Akarvardar, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 7, 2022, as Appl. No. 17/859,721.
Prior Publication US 2024/0013042 A1, Jan. 11, 2024
Int. Cl. G06N 3/08 (2023.01); G06F 7/544 (2006.01)
CPC G06N 3/08 (2013.01) [G06F 7/5443 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A pipelined processing core of an artificial intelligence (AI) accelerator, the pipelined processing core comprising:
a first processing core configured to have a weight stationary dataflow, wherein the first processing core includes:
a matrix array of processing elements (PEs) arranged in columns and rows, each of the PEs configured to perform a multiplication and accumulation (MAC) operation based on an input and a weight;
a second processing core configured to have an input stationary dataflow, the second processing core configured to receive an output from the first processing core, wherein the second processing core includes:
a column of PEs configured to perform MAC operations.