US 12,437,140 B2
Layout structure of clock tree circuitry and forming method thereof
Yingdong Guo, Hefei (CN); Jing Xu, Hefei (CN); Wei Jiang, Hefei (CN); and Xue Shan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 8, 2022, as Appl. No. 17/805,921.
Application 17/805,921 is a continuation of application No. PCT/CN2022/074498, filed on Jan. 28, 2022.
Claims priority of application No. 202111656065.8 (CN), filed on Dec. 30, 2021.
Prior Publication US 2023/0214572 A1, Jul. 6, 2023
Int. Cl. G06F 30/396 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 21/00 (2006.01); H01L 25/00 (2006.01)
CPC G06F 30/396 (2020.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 21/00 (2013.01); H01L 25/00 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method of forming a clock tree layout, comprising:
arranging a divider module layout, wherein the divider module layout is configured to receive a first clock signal, and divide the first clock signal, and obtain a plurality of second clock sampling signals phase-associated;
arranging a phase module layout, wherein the phase module layout comprises a first quantity of phase modules disposed in a first preset direction, the phase module is configured to generate a second clock signal based on a correspondingly connected second clock sampling signal, and the phase modules are symmetrically distributed with respect to the divider module layout; and
arranging wires on the phase module layout and/or the divider module layout, and forming a wire pattern layer, wherein the wire pattern layer is configured to electrically connect a divider module in the divider module layout and a corresponding phase module, and a difference between phases of any two of the second clock signals falls within a preset precision range.